1) A MOD-16 ripple counter is holding the count 10112. What will the count be af
ID: 2990844 • Letter: 1
Question
1) A MOD-16 ripple counter is holding the count 10112. What will the count be after 31 clock pulses?
A) 11002 B) 10112 C) 10102 D) 10012
2) Which group of logic devices represents the minimum hardware required for a MOD 64 synchronous counter?
A) six flip-flops, four AND gates B) four flip-flops, two AND gates
C) five flip-flops, three AND gates D) seven flip-flops, five AND gates
3) A common characteristic of ALL shift-register counters is:
A) they use fewer flip-flops than binary counters.
B) they require more decoding gates than do binary counters.
C) they all use feedback where the last flip-flop output is someway connected back to the first
flip-flop.
D) they count in true binary form.
4) A primary advantage of using J-K flip-flops in asynchronous counter circuits is their ability to:
A) toggle on the clock if the J-K inputs are held HIGH.
B) toggle on the clock if the J-K inputs are held LOW.
C) toggle on the clock if the PRESET and CLEAR inputs are held LOW.
D) toggle on the clock if the PRESET and CLEAR inputs are held HIGH.
5) An asynchronous IC counter has clock inputs labeled (CP0)' and (CP1)'. The overbars indicate the clock inputs are activated by a:
A) NGT. B) PGT. Note, there is a par above (CP0)' and (CP1)'
6) The asynchronous presetting of parallel counters to a specific count normally requires the use of the:
A) PL' and the J-K inputs. B) PL', PRESET, and CLEAR inputs.
C) clock and the J-K inputs. D) clock, PRESET, and CLEAR inputs.
7) Asynchronous down counters:
A) require that each flip-flop change states with each input clock pulse.
B) require that the MSB and LSB flip-flops change states with each input clock pulse.
C) require that the MSB flip-flop change states with each input clock pulse the same as an up counter.
D) require that the LSB flip-flop change states with each input clock pulse the same as an up counter.
8) How many stages would be required for a cascaded BCD counter to provide a decimal count of 9,999?
A) 4 B) 6 C) 5 D) 3
9) When designing a digital clock system using 60 Hz line frequency, the first two major stages should include:
A) a pulse shaper circuit and a MOD 60 counter.
B) a MOD 60 counter and BCD counter.
C) a MOD 2 and BCD counter.
D) a pulse shaper circuit and a BCD counter.
10) A major advantage of the synchronous counter over the nonsynchronous counter is its ability to:
A) operate at higher frequencies.
B) operate with no external circuitry.
C) operate at lower frequencies.
D) operate with its J-K inputs tied permanently HIGH.
Explanation / Answer
1==c
2==a
3==d
4==c
5==b
6==d
7==d
8==a
9==d
10==a
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