Finite State Machines 1) Design a Moore type state machine that has two inputs (

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Finite State Machines

1) Design a Moore type state machine that has two inputs (X and Y) and one output (Z). This machine asserts the output (Z=1) one clock period after the inputs have been equal for the previous two clock cycles otherwise Z=0. Label the states A (the reset state), B, C, etc. Use state encoding starting with 00, then 01, 10, etc. Show the state diagram, state table, minimized equations in SOP form, and the schematic. 2) Design a Mealy state machine that checks a serial input for even parity. The output Z=1 for even parity (an even number of 1 s), Z=0 for odd parity (an odd number of 1 s). Show the state diagram, state table. You do not have to show the equations or schematic. 3) Given the following state table draw the state diagram also determine the minimized equations for the next state in SOP form and draw a schematic. A and B are for the present state and NA and NB are for the next state. This is a Moore machine with the outputs equal to the assigned state values. Next State Present State X=0 X=1 A B NA NB NA NB 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 0 1 1 1 1 0 0 1

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