One of the engineers just came up with the following suggestion during a design

Question

One of the engineers just came up with the following suggestion during a design meeting to speed-up the execution.

The proposed new approach:

%u201CWe should add more hardware resources to Figure 4.51 so we can allow both paths, following a branch instruction and not following a branch instruction, to be followed.  We calculate the PC for both taking the branch and not taking the branch.  Then we fetch both instructions using the redundant resources.  When the branch instruction result is known, we decide which instruction is to be followed while the other is flushed.%u201D

As the Chief Designer,

(a) please give 2 reasons on why this approach may not work, and

(b) are there any data hazards (i.e., both branches writing into the same register before we flush out one instruction path)?

Use the following instruction sequences for this discussion:

36  add $s1, $s2, $s3

40  beq $s1, $s4, 4

44  add $s1, $s1, $s5

48  add $s1, $s1, $s6

52  add $s1, $s1, $s7

56  add $s1, $s1, $s8

60  add $s1, $s1, $s9

64  add $s1, $s1, $s10

Explanation / Answer

a) two reasons :

1) It will not work well with caches.

There are 2 cases, one fall through and the other with a jump, so the jump requires to an instruction fetch from not the nearest place, so the locality of reference might not hold, so you have one branch missing and other hitting the cache,

so depending on the implementation you might have to wait both the branches till you get the data, in this case the small gain of not flushing out the cache(~5cycle) is easily wiped out by the cache miss (100s of cycles)

in the other case you have a coherence problem, if I let one execution go ahead, but I had to take the different branch then it might already have overwritten the data which I need thus making the state inconsistent.

2) What if one has 2 conditional branchs one below the other, now what? we will require additional hw for 4 executions in parallel so more hw and problems

b)

3) Data hazards : What if one overwrites the data of the other

Generally this wont occur , it can in 2 cases :

i. Caches

ii. Variable length pipelines

i. Caches : already written about it up, if one incurs a cache miss then other might overwrite the regs and have error.

ii. Variable length pipelines : if one instruction requires only 4 microops while other requires 10muops (this can be the case in modern pipelined processors) then one might have already written to the reg, before the other guy reads from it. (this is dependent on the depth of the pipeline if the depth is small like 5 then there will not be any data hazards but if its big like 10-13 again modern processors are this deep) then hazards will occur since we have like 10 instructions in the pipeline at the same time.

comment if you have any doubts

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