In Verilog (2001) construct a 4x4 register file. Please add comments in the code
ID: 3593174 • Letter: I
Question
In Verilog (2001) construct a 4x4 register file. Please add comments in the code if there is anything unclear. I would like to see the structural and behavior level descriptions, and a test bench. Please see the attached image as a little reference.
Register File (2 read ports, 1 write port) Pq.2 module regfile(input clk, input we3, input [4:0] ra1, ra2, wa3, input [31:0] wd3, wiothoutput [31:0] rd1, rd2); reg 131:0 r 31:01epth always @(posedge clk) assign rd1 = (ral ! :0) ? rTra1] : 0; 1/read 1 outside of assign rd2+ (ra2 != 0) ? rtlra2] : 0; 1/read 2-always 112-D (32x32) array //write Endmodule INote: rffo1 is always 0!Explanation / Answer
// Verilog description for an 4 x 4 register file
module regfile4x4a
(input clk,
input write,
input [2:0] wrAddr,
input [3:0] wrData,
input [2:0] rdAddrA,
output [3:0] rdDataA,
input [2:0] rdAddrB,
output [3:0] rdDataB);
reg [3:0] reg0, reg1, reg2, reg3;
assign rdDataA = rdAddrA == 0 ? reg0 :
rdAddrA == 1 ? reg1 :
rdAddrA == 2 ? reg2 :
rdAddrA == 3 ? reg3 : 0;
assign rdDataB = rdAddrB == 0 ? reg0 :
rdAddrB == 1 ? reg1 :
rdAddrB == 2 ? reg2 :
rdAddrB == 3 ? reg3 : 0;
always @(posedge clk) begin
if (write)
case (wrAddr)
0: begin
reg0 <= wrData;
end
1: begin
reg1 <= wrData;
end
2: begin
reg2 <= wrData;
end
3: begin
reg3 <= wrData;
end
endcase
end
endmodule
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