5.1 Consider the circuit shown in Figure E5.1. Show the design is that of a 1- b
ID: 3599809 • Letter: 5
Question
5.1 Consider the circuit shown in Figure E5.1. Show the design is that of a 1- b it full adder by forming the truth tables and equations of the circuit.
5.3 Compute C6 of the carry- lookahead generator equations.
5.6 Show the design of a 2- bit magnitude comparator from 1- bit magnitude comparators.
5.8 An n- bit magnitude comparator can be designed from 1- bit magnitude comparators with enable lines. Show the design of a 5- bit magnitude comparator from 1- bit magnitude comparators with enable lines. Hint the design can be accomplished with five 1- bit comparators and 2 additional gates.
In addition, compute the delays C1, C2, C3 and in general Cn when the design of an adder is
completed as a carry-lookahead adder as given in Figure 5.2.2 for the case of a 4-bit carry-lookahead adder.Assume the gate delays are2 ns, for AND and OR gates (independent of the number of inputs) and 3 ns for XOR gates.
AB CiExplanation / Answer
package com;
import java.io.BufferedReader;
import java.io.FileReader;
import java.io.IOException;
public class ReadFileExample1 {
private static final String FILENAME = "D:\test.txt";
public static void main(String[] args) {
BufferedReader br = null;
FileReader fr = null;
try {
//br = new BufferedReader(new FileReader(FILENAME));
fr = new FileReader(FILENAME);
br = new BufferedReader(fr);
String sCurrentLine;
while ((sCurrentLine = br.readLine()) != null) {
System.out.println(sCurrentLine);
}
} catch (IOException e) {
e.printStackTrace();
} finally {
try {
if (br != null)
br.close();
if (fr != null)
fr.close();
} catch (IOException ex) {
ex.printStackTrace();
}
}
}
}
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.