Clock Divider (4 points) You are to design a Clock Divider using D-Flip-Flops. A

Question

Clock Divider (4 points)
You are to design a Clock Divider using D-Flip-Flops. A D-Flip-Flop can be used as a “Divide-by-2” by connecting the Q’ output to the D input. By doing this, the Q output will be exactly ½ the frequency of the incoming clock. The output of this “Divide-by-2” circuit can be used as the clock input to another “Divide-by-2” circuit to achieve a “Divide-by-4”, etc….
Use this topology to construct a selectable Clock Divider with possible divide choices of 2, 4, 8, and 16. This should take 4 D-Flip-Flops with each Q output going into a 4-to-1 Mux.

I want this design in VHDL lang.

Explanation / Answer

try this module for Clock Divider in VHDL lang. entity c1hz is port( clk:in bit; clkout:out bit); end c1hz; architecture behavior of c1hz is begin process(clk) variable cnt : integer range 0 to 383; begin if(clk'event and clk='1') then if(cnt=383)then cnt:=0; clkout

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