Consider a processor in which a two-word instruction is stored at location 100 w

Question

Consider a processor in which a two-word instruction is stored at location 100 with its address field at location 101 as shown below.



Memory
Registers Address Content

PC =100 100 Load to AC; Mode
101 Address = 600
R1 = 300 102 Next instruction
: :
XR = 200 200 300
: :
BR = 300 300 700
: :
AC = ? 400 200
: :
500 100
: :
600 400
: :
702 500
: :
800 900
: :
900 800

The first word of the instruction specifies the operation code and mode; the second word specifies the address part.
The values of the program counter (PC register), a general register (R1), the index register (XR), the base register (BR), and certain addresses in memory are as shown below.

Evaluate the effective address and the value that is loaded into the AC for the following addressing modes:

Addressing Mode Effective address Value of the operand loaded into the AC
a) Immediate
b) Direct addressing
c) Indirect addressing
d) Register
e) Register indirect
f) Relative address
g) Base register addressing
h) Indexed addressing

Explanation / Answer

Addressing Mode Effective address Value of the operand loaded into the AC a) Direct Address PC+1=350+1=[351] 833 b) Immediate Address PC+1=350+1=351 400 c) Indirect Address PC+1=350+1=[[351]] 900 d) Relative Address 350+2+[350+1]=352+400=752 189 e) Indexed Address 125+[350+1]=125+400=525 735 f) Register R1=834 834 g) Register Indirect [R1]=[834] 950 h) Autoincrement [R1]=[834] 950 i) Autodecrement [R1-1]=[833] 900 Registers Memory PC = 350 R1 = 834 XR = 125 AC Address Memory 350 Load to AC | Mode 351 Address = 400 352 Next Instruction 833 900 834 950 400 833 900 456 752 189 525 735 Find a reference to a processor that implements an instruction pipeline and describe some of its key features. You should say how many segments are used and whether the processor is CISC or RISC, among other issues. The ARM processor is a RISC processor which features a 5 stage, 4 segment pipeline. Pipeline description • Advanced processing of instruction fetch and branch prediction - unblocks branch resolution from potential memory latency-induced instruction stalls. • Up to four instruction cache line prefetch-pending - further reduces the impact of memory latency so as to maintain instruction delivery. • Between two and four instructions per cycle forwarded continuously into instruction decode - ensures efficient superscalar pipeline utilization. • Fast-loop mode - provides low power operation while executing small loops. • Superscalar decoder - capable of decoding two full instructions per cycle. • Speculative execution of instructions - enabled by dynamic renaming of physical registers into an available pool of virtual registers. • Increased pipeline utilization - removing data dependencies between adjacent instructions and reducing interrupt latency. • Virtual renaming of registers - accelerating code through an effective hardware based unrolling of loops without the additional costs in code size and power consumption. • Any of the four subsequent pipelines can select instructions from the issue queue - providing out of order dispatch further increasing pipeline utilization independent of developer or compiler (page 6) Reference: The ARM Cortex-A9 Processors, Whitepaper Be sure to include citations. Determine the number of clock cycles that it takes to process 500 tasks in a 8-segment pipeline. See Mano, pg 329, 9-3. k = 8 segments n = 500 tasks cycles = (k+n-1) = 8+500-1 = 507 cycles A non-pipeline system takes 50 ns to process a task. The same task can be processed in a 8-segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 100 tasks. What is the maximum speedup that can be achieved? See Mano pg 329, 9-4 S=(n*t_n)/((k+n+1) t_p )=(100*50)/((8+100-1)*10)=5000/1070=4.67 S_max=t_n/t_p =50/10=5 Section 3 Pick a number between 16 and 128 - call this A A = 112 Pick another number between 5 and 10 - call this T T = 8 The numbers you select should be different from those selected by other students. Explain how a direct mapping cache would work with a computer using A bits for memory addressing and T bits for a direct mapping cache. The A bit memory address will be divided into two fields, T bits for the index field and A-T bits for the tag field. Given that A = 112 and T = 8, the index field is 8 bits and the tag field is 104 bits. The direct mapping cache organization uses the full 112 bit address to access the main memory and the 8 bit index to access the cache. How many words will the cache have? 28 = 256 words Ram sizing: How many 256x8 RAM chips are needed to provide a memory capacity of 16,384 bytes? 256x8 RAM chips have 256 bytes per chip so 16384/256 = 64 RAM chips How many lines of the address bus must be used to access 16,384 bytes of memory? How many of these lines will be common to all the chips? 14 bits are necessary to specify each byte of memory (214 = 16384), each chip has 256 1 byte addresses, so 8 lines will be common to all chips (28 = 256). How many lines must be decoded for chip select? Specify the size of the decoders. 6 bits are necessary to specify the specific chips (26 = 64) A computer uses RAM chips of 1024x1 capacity How many chips are needed, and how should their address lines be connected to provide a memory capacity of 4096 bytes? 1024x1 * 8 (to make each a byte) * 4 = 4096 bytes, so 8*4 = 32 chips How many chips are needed to provide a memory capacity of 64K bytes? Explain in words how the chips are to be connected to the address bus. 4096 * 4 =16kB 32 chips (for 4096 bytes) * 4 = 128 chips to get 64kB Each chip must be connected to the address bus to take the lines necessary to determine which memory location is being addressed. The chips are connected in groups of eight, so that each of these groups form one word. This means that the design is repeated eight fold for the chips, such that for a given memory location each bit of the word is stored (as the chips are of x1 construction). How many tag bits are needed in a direct mapped cache of 1024 words in a computer with 1M words? It requires 20 bits to address 1M words, so the tag size would be 1024-20 = 1004.

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