Consider a processor that has a separate data and insturction cache. The data ca
ID: 3758202 • Letter: C
Question
Consider a processor that has a separate data and insturction cache.
The data cache has a 92% hit rate and a 2-cycle hit latency. 30% of instructions are loads or stores. Assume that the latency to memory and the cache miss penalty toghether is 124 cycles.
The Instruction cache has a hit rate of 90% with a miss penalty of 50 cycles.
Assume the base CPI using a perfect memory system is 1.0 and that instruction cache misses and data cache misses never occur at the same time.
a) Calculate the additional CPI due to the instruction cache stalls.
b) Calculate the additional CPI due to the data cache stalls.
c) Calculate the overall CPI for the Machine.
Explanation / Answer
given that , for instruction cache
hit rate = 90%= 90/100=0.9
miss rate= 1-0.9=0.1
miss penalty=50 cycles
Assume I= number of instructions per the program.
instruction cache stalls= I miss rate X miss penalty
= I 0.1 50
= 5 I
The additional CPI , due to instruction cache stalls is 5 cycles(since I is constant).
for data cache,
hit rate = 92 % = 92/100= 0.92
miss rate = 1-0.92=00.8
miss penalty=124 cycles
percentage of loads and stores= 30 %
Data cache stalls= I ( hit latency hit rate + loads and stores miss rate miss penalty)
= I ( 0.92 2 + 30 % 0.08 124)
= I (1.84 + 2.976)
=I 4.816
= 4.82 I
The additional CPI , due to data cache stalls is 4.82 cycles.
c)
overall CPI for the machine = CPI (perfect) + additional CPI due to data cache stalls + additional CPI due to instruction cache stalls
= 1 + 4.82 + 5
= 10.82 11 cycles
Therefore, the overall CPI for the machine is 11 cycles.
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