Behavioral Verilog (Named alu4_beh): Design an ALU (see Figure 1) in behavioral

Question

Behavioral Verilog (Named alu4_beh): Design an ALU (see Figure 1) in behavioral Verilog. You can define all of the functionality in a single module.

Design Constraints: The design must properly function given the following constraints:

- The A input is named A_in and is 4 bits wide.

- The B input is named B_in and is 4 bits wide.

- The Select input is named SEL_in and is 2 bits wide.

- For the Structural models, you may only use the behavioral components you created (adder, inverter, mux, etc) or Verilog Primitives.

Explanation / Answer

working verilog code for the same.

module alu4_beh(
A,B,S,Y);
input [3:0] A;
input [3:0] B;
input [1:0] S;
output [3:0] Y;

always @*
begin
if (S==2'b00)
begin
Y=~A;
end
else if (S==2'b01)
begin
Y=A+B;
end
else if (S==2'b10)
begin
Y=A-B;
end
else
begin
Y=A+A;
end
end

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