Using the following \"4-bit binary counter with parallel load\", construct the b
ID: 3682069 • Letter: U
Question
Using the following "4-bit binary counter with parallel load", construct the block diagram the following counters: A 5-bit binary counter that counts even numbers from 0 to 30 (decimal) that is 00000 to 11110 (binary) A 5-bit binary counter that counts odd numbers from 1 to 31 (decimal) that is 00001 to 11111 (binary) An 8-bit binary counter that counts from 0 to 127 (decimal) that is 00000000 to 01111111 (binary) Note: The counter shown in picture above is the same counter that is described in Figure 7-14 of the text book. The functionality of the Load and Count pins are as follows: When Load = 1 the inputs on D0 to D3 are loaded to the counter outputs Q0 to Q3. When Count = 1 the counter continues to count and when Count = 0 the counter stops.Explanation / Answer
This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because
presetting is synchronous, a low logic level at the load (LOAD
) input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT.
The clear function is synchronous, and a low logic level at the clear (CLR
) input sets all four of the flip-flop outputs
to low after the next low-to-high transition of the clock, regardless of the levels of ENP and ENT. This
synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to the clear input to
synchronously clear the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications, without
additional gating. This function is implemented by the ENP and ENT inputs and an RCO output. Both ENP and
ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, produces a
high-logic-level pulse while the count is 15 (HHHH). The high-logic-level overflow ripple-carry pulse can be used
to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
The SN74F163A features a fully independent clock circuit. Changes at ENP, ENT, or LOAD
that modify the
operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter
(whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the setup and hold
times.
ORDERING INFORM
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