What would the overall miss ratio be for the following address stream on the dir

Question

What would the overall miss ratio be for the following address stream on the direct mapped cache? Assume the cache starts out completely invalidated.

read 0x00
read 0x04
write 0x08
read 0x10
read 0x08
write 0x00

Cache hierarchy

You are building a computer system with in-order execution that runs at 1 GHz and has a CPI of 1, with no memory accesses. The memory system is a split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32 KB each, with a block size of 64 bytes.

The memory system is split L1 cache. Both the I-cache and the D-cache are direct mapped and hold 32KB each, with a block size of 64 bytes.

The I-cache has a 2% miss rate, and the D-cache is a write-through with 5% miss rate.

The hit cycles for both the I-cache and the D-cache take 1 cycle (1 cycle takes 1 ns).

The L2 cache is a unified write-back with a total size of 512 KB and a block size of 64 bytes.

The hit cycle of the L2 cache is 15 cycles. The local hit rate of the L2 cache is 80%.

An L2 data write miss takes extra 15 ns.

Given: Hit time=Hit Rate*Hit Cyles

L2 miss penalty = 100nsec

Compute the AMAT for both instruction and data memories

Explanation / Answer

read 0x00 M
read 0x04 M
write 0x08 M
read 0x10 M
read 0x08 H
write 0x00 M

Miss ratio = 5/6 = 0.8333

b)

Assume a L2-miss will cause the memory transfers to both of L1 and L2.
Cycle time to transfer one bus word (64b) = 1/100MHz = 10ns
Time to transfer memory block to cache way (64B): 64B/64b * 10ns = 80ns

For Instruction:

AMAT = 98%*1ns (L1 instruction hit)
+2%*( (L1 instruction miss)
80%*15ns (L2 instruction hit)+20%*(20ns+80ns)) (L2 instruction miss: access latency + transfer)
= 1.62 ns

For data:
AMAT = 95%*1ns (L1 data hit)
+ 5%*( (L1 data miss)
80%*15ns (L2 data hit) +20%*(15ns+20ns+80ns)) (L2 data miss: write miss + latency +transfer)
= 2.7ns

Overall AMAT = 1.62 + 2.7 = 4.32ns

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