When processor designers consider a possible improvement to the processor datapa
ID: 3714441 • Letter: W
Question
When processor designers consider a possible improvement to the processor datapath, the decision usually depends on the cost/performance trade-off. In the following problems, assume that we are starting with a datapath from Figure 1, where Block Delay (ps I-Mem Add Mux ALU Regs 400 100 20 160 200 500 100 D-Mem Control blocks Note that this is a single-cycle processor, so every instruction takes one cycle to execute Consider the addition of a multiplier to the ALU. This addition will add 120 ps to the latency of the ALU The result leads to fewer instructions executed since we will no longer need to emulate the MUL instruction. 1.1) What is the clock cycle time with and without this improvement? (10 pts) 1.2) If this improvement can result in 15% fewer number of instructions executed as we no longer need to emulate the MUL instruction. What is the speedup achieved by adding this improvement? Does this increase or decrease the performance? (10 pts) 1.3) If we want to achieve a speedup that is 2 1.2 by adding this MUL operation to ALU, what percentage of instructions should be reduced at least? (10 pts)Explanation / Answer
Solution:
1.1)
With improvement:
clock cycle time = 400+100+20+160+200+500+100+120 = 1600 ps
Without improvement:
clock cycle time = 400+100+20+160+200+500+100 = 1400 ps
1.2)
Then the clock cycle time will decrease by 15 % which means
0.85*1600= 1360
speedup = 1400/1360= 1.02941176471
1.3)
To get the speedup greater than 1/2 we need
the clock cycle time with improvement to be
1400/1.2 = 1166.66666667 ps
1166.66666667/1600= 0.72916666666 which is 72.912 %
improvement needs to be of
100-72.912 = 27.088 %
I hope this helps if you find any problem. Please comment below. Don't forget to give a thumbs up if you liked it. :)
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.