The classic five-stage pipeline MIPS architecture is used to execute thecode fra
ID: 3718100 • Letter: T
Question
The classic five-stage pipeline MIPS architecture is used to execute thecode fragments. Assume the followings:
Register write is done in the first half of the clock cycle; register read is performed in the second half of the clock cycle,
Branches are resolved in the fourth stage of the pipeline and the architecture does not utilize any branch prediction mechanism
Forwarding is not supported.
Assuming there is no dependence other than one(s) given in the code, show the pipeline diagram.
Clock Cycle à
1
2
3
4
5
6
7
8
9
10
11
12
13
add R1, R2, R3
add R1, R1, R4
add R1, R1, R5
Clock Cycle à
1
2
3
4
5
6
7
8
9
10
11
12
13
add R1, R2, R3
add R1, R1, R4
add R1, R1, R5
Explanation / Answer
Please find below the pipeling process
Clock Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 add R1,R2,R3 IF RR ALU MEM WB add R1,R1,R4 IF RR ALU MEM WB add R1,R1,R5 IF RR ALU MEM WBRelated Questions
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