8.8 Redesign the arbitrary counter of Section 8.5.3 using a mod-5 counter and sp
ID: 3736629 • Letter: 8
Question
8.8 Redesign the arbitrary counter of Section 8.5.3 using a mod-5 counter and special output decoding logic. Derive the VHDL code for this design.
8.5.3 Arbitrary-sequence counter A sequential counter circulates a predefined sequence of states. The next-state logic de termines the patterns in the sequence. For example, if we need a counter to cycle through the sequence of "000", "011", "110", "101" and "111", we can construct a combinational circuit with a function table that specifies the desired patterns, as in Table 8.1. The VHDL code is shown in Listing 8.11. Again, the code follows the basic block diagram of Figure 8.5. A conditional signal assignment statement is used to implement the function table. Listing 8.11 Arbitrary-sequence counter library ieee; use ieee. std_logic.1164. all;Explanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counter_fsm_ex is
port(
CLK, RESET : in std_logic;
OUT1 : out std_logic_vector (2 downto 0)
);
end counter_fsm_ex;
architecture Behaviour of counter_fsm_ex is
signal Next_Count, Count : std_logic_vector (2 downto 0);
begin
Next_Count = Count + 1;
process (CLK, RESET)
begin
if (RESET = '1') then -- asynchronous active high reset
Count <= "000";
elsif(CLK'event and CLK = '1') then
if (Next_Count == "100") then -- Counter will fold to 0 when it next_count >= X
Count <= "000";
else
Count <= Next_Count;
end if;
end if;
end process;
OUT1 <= "000" when Count = "000" else
"011" when Count = "001" else
"110" when Count = "010" else
"101" when Count = "011" else
"111" when Count = "100" else
"000";
end Behaviour;
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