Computer Architecture: Memory and Cache, if your answer is not sure, please indi

Question

Computer Architecture: Memory and Cache, if your answer is not sure, please indicate NOT SURE Thanks

(Q1) For a direct-mapped cache with a 32-bit address, the following bits of the address are used to access the cache:

Tag: 31-10 // Index: 9-5 // Block Offset: 4-0 // What is the block size (in words)?

(a) 32 words

(b) 16 words

(c) 5 words

(d) 8 words

(Q2) For a direct-mapped cache with a 32-bit address, the following bits of the address are used to access the cache:

Tag: 31-12 // Index: 11-6 // Block Offset: 5-0 // How many blocks does each single set have?

(a) 64

(b) 32

(c) 8

(d) 16

Explanation / Answer

Q1) answer is d) 8 words

Cache line size = 2offset bits = 25 bytes = 23 words = 8 words

Q2) answer is b) 32

Entries = 2index bits = 25 lines

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