Consider a machine which implements an ISA in which every instruction is 32 bits

Q: Consider a machine which implements an ISA in which every instruction is 32 bits

A) 27 = 128 unique opcodes can be represented by 7 bits. B) SR can use any of the 16 registers so the minimum number of bits required = 4 as 24 = 16 C) The remaining bits for IMMVAL = 32 -(7+4+4) = 17 bits So it can have a range of unsigned values from 0 to 131071(217 - 1) Opcode = 7 bits DR = 4 bits SR = 4 bits IMMVAL = 17 bits

ID: 3797557 • Letter: C

Question

Consider a machine which implements an ISA in which every instruction is 32 bits long and has the following format:

Where DR = Destination Register, SR = Source Register, and IMMVAL = Immediate Value. The fields DR, SR are represented using the same number of bits.

If there are 7 bits for the opcode and 16 registers,

A.) How many unique opcodes can be represented?

B.) What is the minimum number of bits required for the source register (SR) field?

C.) If IMMVAL represents an unsigned value, what is the range of values (in decimal) that can be represented using the immediate value field?

opcode DR SR MMAL

Explanation / Answer

A) 27 = 128 unique opcodes can be represented by 7 bits.

B) SR can use any of the 16 registers so the minimum number of bits required = 4 as 24 = 16

C) The remaining bits for IMMVAL = 32 -(7+4+4) = 17 bits

So it can have a range of unsigned values from 0 to 131071(217 - 1)

Opcode = 7 bits DR = 4 bits SR = 4 bits IMMVAL = 17 bits

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Consider a machine which implements an ISA in which every instruction is 32 bits

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