2. [24 marks] 1) Compulsory misses occur the first time a program touches a cach

Question

 2. [24 marks] 1) Compulsory misses occur the first time a program touches a cache line.  2) Conflict misses occur when more than 'm' lines map to the same set in an m-way set-associative cache.  3) Capacity misses occur when a program's working set exceeds the cache capacity.  It is hard to do much about compulsory misses, but both conflict and capacity misses are affected by the geometry parameters of a cache: its capacity, its associativity (wayness), and its cache-line size.  a) [8 marks] If we increase the capacity 'S' of the cache, but keep the other two parameters constant, will i) conflict misses, and ii) capacity misses, increase or decrease?  Explain.  Also, is there a downside to larger caches? Explain.  b) [8 marks] If we increase the associativity (wayness) 'm' of the cache, but keep the other two parameters constant, will i) conflict misses, and ii) capacity misses, increase or decrease?  Explain.  Also, is there a downside to increased associativity?  Explain.  c) [8 marks] If we increase the cache-line size 'L' of the cache, but keep the other two parameters constant, will the miss rate increase or decrease i) for programs with a high spatial locality, and ii) for programs with low spatial locality?  Explain. 

Explanation / Answer

M-Way Set Associative Cache:

Number of lines in each set would be M therefore each K-block of main memory can now be mapped into any one of a set of M cache blocks.

Example:
Main Memory Size = 2KB
Block Size = 8 B
Cache Size = 64 B
Set Size = 2 (2-way set associative cache)

Number of blocks in Main Memory = 2KB/8B = 2^11 / 2^3 = 2^8 = 264 blocks
Number of sets in cache = cache size / set size = 64B/(2*8)B = 4
Memory address size = 11 (Tag + index + offset) bits

Index size: no of sets (4) = 2^2 = 2 bits
offset size : block sise (8B) = 2^3 = 3 bits
therefore tag size : 6 bits

264 / 4 = 2^6 = 6 bits for tags

Answer a) If we increase the cache size (64 B) above in example in 2-way set associative cache then number of set will increase and number of block mapped to the same set will decrease and hense conflict miss will decrease and as the number of sets are increasing and the there is a lot of room for blocks the chances of
compulsory misses will also decrease.

Answer b) If we increase the associativity (wayness) m in above example (3-way) of the cache then number of set will decrease and number of blocks mapped to the same set will increase
and hense conflict miss will decrease and compulsory misses will gets decrease.

Answer c) If we increase the cache line size 'L' of the cache then number lines in each set will decrease hence in case of:

   1) High Spatial Locality: If the continuous request is for different blocks then it might be present in the same set     as conflict miss will decrease and the compulsory miss also get decrease.

   2) Low Spatial Locality: If the continuous request is for same of sequential blocks then increasing the line size will increase the conflict miss and compulsory miss also gets increase.

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