Create a function parity that takes as input a word of type std_logic_vector (of

Question

Create a function parity that takes as input a word of type std_logic_vector (of arbitrary length) and returns a value of type std_logic. The returned value should be: '0' is there are an even number of '1's in the word '1' if there are an odd number of '1's in the word Below is a piece of VHDL code that you can use to test your function. Add your function to the code and simulate to check that your code is giving the correct result. Show your code and the simulation results. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test_parity is end test_parity; architecture Behavioral of test_parity is signal data: std_logic_vector (3 downto 0):="0000"; signal pl, p2, p3, p4: std_logic; begin pt: process begin wait for 10 ns; data

Explanation / Answer

Try this code -

function parity(s : std_logic_vector) return std_logic is
variable temp : integer := 0;
variable ans: std_logic := '0';
begin
for i in s'range loop
if s(i) = '1' then temp := temp + 1;
end if;
end loop;
  
if (temp mod 2) = 0 then
   ans :='0'
else
   ans :='1'
end if;

  
return ans;
end function parity;

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