Assume a 5 stage processor like the one discussed in class and text. Answer the

Question

Assume a 5 stage processor like the one discussed in class and text. Answer the following questions assuming the 5 stages have the following What is the single cycle time for this processor? _____ If the 5 stages are pipelined what is the cycle time for this processor? _____ How long will a single instruction take to complete given the 5 stage pipeline? ______ If the company develops faster memories and reduces the 1M latency to 175 ps and the Data Memory latency 200 ps what is the speedup for the updated pipelined processor (all other latencies remain the same)? ____)

Explanation / Answer

1.In single cylce every insruction need to be executed indepently so time will be (225+150+90+250+90)=705ps.

2.When the 5 stages are pipelined then the stage having high latency will have equal to cylce time=250ps+some latency for register for data dependency.

3.In both pipeline and non-pipeline the single Instruction time will be same i.e. =5*250=750ps or (k+n-1)*Cycle time => put n=1 then we get k*cycle time i.e no of stages *cycle time(k=pipeline stages, n=no of instructions

4. speedup=old cycle time/new cylce time=250/200=5/4=1.25

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