In the following, a number of acronyms are used to refer to different components

Question

In the following, a number of acronyms are used to refer to different components of virtual memory. These are: Consider a processor with 32-bit virtual addresses. Assuming a 4 KB (2^12 bytes) page size, 2 byte page table entries (which include one valid bit and one dirty bit), answer the following: (a) What is the capacity of the virtual memory in terms of bytes? It is OK to leave your answer as a number raised to an exponent. (b) What is the maximum capacity of the physical memory this virtual memory system can support? Express your answer in bytes. Show your work. (c) What is the memory cost to store the whole page table in the memory? Express your answer in bytes. Show your work. The initial page table in the memory: (e) What is the final state of page table after memory accesses in (d)? Fill out the following table to show your answer. (d) Consider a fully associative TLB with 4 virtual-to-physical page translation entries and the Least-Recently Used (LRU) method is used for the replacement strategy. The initial state of TLB is given in the first table. The initial state of page table is shown in the next page. If pages must be brought in from disk, increment the largest current page number in the table. For example, the next page fetched for the initial page table would be 0xD. We have following memory accesses Please update the TLB entry for each memory access by filling out the following TLB state tables. Please use hexadecimal numbers for VPN and PPN. Use "1" for valid and "0"for invalid.

Explanation / Answer

Hi,

Please find the answer with detail explantion below:-

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Given:-

32 bit addressing for virtual address

12 byte page size,2 byte page table entry

4KB PAGE

Questions to be solved:-

Bits required to address is 32

Hence total addressing can done for 2^32 locations

Now since answer needs to be in bytes then:-

Total capacity of virtual memory =2^32=4GB logical address space size (virtual memory size)

                                       

                Given :-

                Each page table entry has 2 bytes

                 i.e 2*8 =16 bits

                 physical address = 2^16 address=2GB physical memory address space size

VIRTUAL MEMORY SIZE=2^32

PHYSICAL MEMORY SIZE=2^16

Hence to store whole page table in main memory it will take almost half of the total page table faults.

Hence the whole fetch and load operation involves two physical memory accesses:

This doubles the latency for logical memory accesses

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Please let me know in case of clarification.

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