Given a 2-way Set Associative cache with 4 lines using LRU replacement within ea
ID: 3825426 • Letter: G
Question
Given a 2-way Set Associative cache with 4 lines using LRU replacement within each set. The word size is one byte, there is one word per block, and the main memory capacity is 16 bytes. Suppose the cache is initially empty and then the following addresses are accessed in the order listed: {3,4,3,7,7,12,4,8,3,12,7,9}. How many bits are in the tag field? (i.e. the tag itself not including any counter bits) After execution of all of the above references, what are the final contents of the cache ? State your answer as a set of memory addresses whose data resides in cache, e.g. "{3,4,8,12}". For instance, if memory[3], memory[4], memory[8], and memory[12] resided in cache then the answer is stated as "{3,4,8,12}". What is the hit rate? Express your answer as a percent.Explanation / Answer
Answer:
Given: A 2-way Set Associative cache with 4 lines using LRU replacement inside each set. The word
Size is one Byte, here is one word per block, in addition to the main reminiscence ability is 16 Bytes. Assume the
Cache is at first empty and after that the next addresses are access in the arrange listed:
{3,4,3,7,7,12,4,8,3,12,7,9}.
Solution 2.1: How many bits are in the tag field? (I.e. the tag itself not counting any counter bits)
Solution: at this time, 2^w=1 -> w=0. 2^m=1 -> m=0. 2^a=16 -> a=4. The figure of sets is establish by: (4
lines/cache)/(2 line/set)=(2 set/cache)=2 sets so 2^s=2 -> s=1. t=a-s-m-w=4-1-0-0=3.
Solution 2.2: After carrying out of all of the above reference, what are the final inside of the cache?
Solution: on slide 2 of this Study Set., we set up the field indoctrination is [3 bits for tag | 1 bit for set]. So
Writing all the addresses in dual we obtain:
{0011,0100,0011,0111,0111,1100,0100,1000,0011,1100,0111,1001} thus the Lbs. indicates set numbers
as: {1,0,1,1,1,0,0,0,1,0,1,1} with flexible LRU mapping within each set. It is 2-way Set Associative so k=2
Meaning present are two entries per set, label a and b below. The contents of cache are shown below
For each of the four lines from top in the direction of bottom. Replacements are depicting by right arrow. The final cache
Contents are the rightmost entry for each line:
Set 0: entry a: 4à12
Set 0: entry b: 12à8
Set 1: entry a: 3à9
Set 1: entry b: 7
Answer: {7, 8,9,12} listed in any order or reminiscence[7], memory[8], memory[9], and memory[12] listed
In any order.
Solution 2.3: pardon? is the hit rate? Express your answer as a percent.
Solution: The access thread results in {m,m,h,m,h,m,h,m,h,m,h,m} which has 5 hits out of 12 references Thus, h=5/12 = 0.4167= 41.67%. Answer: 41.67% or 41.7% or 41% or 42%
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