Consider a processor with the following features: 35% of the instructions are da

Question

Consider a processor with the following features: 35% of the instructions are data moving instructions (LW/SW etc.) L1 cache hit time: 0.96ns, L1 cache miss rate: 11% For those that miss from L1 cache, an L2 cache will be accessed: L2 cache access time: 3.22ns, L2 cache miss rate: 60% For those that miss from L2 cache, L2 miss penalty/main memory access time: 80ns a. Assume that the L1 hit time determines the clock cycle time. What is the clock rate for this processor? b. What is the AMAT for this processor? c. Assuming a base CPI of 1.0 without any memory stalls, what is the actual CPI considering the delay caused by data memory accesses?

Explanation / Answer

processor with features:

35 % of instructions

L1 cache hit time=0.96ns

L1 cache miss rate=11%

L2 cache accesstime =3.22 ns

L2 cache miss rate=60%

L2 miss penalty/main memory access time =80ns

a)clock rate = 1/( Hit Time(L1))

= 1/(0.96)

=1.04167 GHz

b)AMAT forthis processor:

Average Memory Access Time:

=Hit time +Miss rate * Miss Penalty (ns or clocks)

where, Hit time : is time to access the cache

Miss rate: 1-Hit rate, where Hit rate is fraction found in the cache.

Miss penalty: time to replace a block from lower level.

for a second level cache(L2):

AMAT =Hit Time (L1)+ Miss Rate (L1)* Miss Penalty(L1)

Miss Penalty(L1)= Hit Time (L2) + Miss Rate(L2)*Miss Penalty(L2)

AMAT = 0.96 +0.11 * (3.22 +0.6 *80)

= 0.96+0.11 * (3.22+ 48)=0.96+ 0.11 *51.22

=0.96 + 48.3542

=49.3142 ns

c)A base CPI =1.0 without any memory stalls.

Actual CPI:

Miss cycles =(IC) (Memory Access freq) (Miss Rate)(Main Memory Access/ HitTime (L1))

= IC * (0.35) * (0.11)(80/0.96)= IC * 3.2083

Total Cycles =(1.0) (IC) +Miss Cycles

=4.2083 IC

CPI = Total Cycles/IC = 4.2083

CPU Time with Stalls =(IC) (CPI) (Clock Cycle)

=(IC) (CPI) (Hit Time (L1))

= IC * 4.2083 * 0.96

=IC * 4.0399

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