Research the cache organization of a modern desktop Processor (e.g. Intel curren
ID: 3838036 • Letter: R
Question
Research the cache organization of a modern desktop Processor (e.g. Intel current generation core i processor) and a modern mobile processor and fill out a table same as the table below. List references for your answers.
I.e. find the cache organization of recent desktop cpu and a mobile cpu and compete the figure below with their specifications
Intel Nehalem ARM Cortex-A8 Characteristic split instruction and data caches L1 cache organization Split instruction and data caches 32 KiB each for instructions/data 32 KiB each for instructions/data L1 cache size per Core 4-way 8-way (D) set associative L1 cache associativity 4-way (I), 4-way (D) set associative Approximated LRU L1 replacement L1 block size Write-back, No-write-allocate Write-back, Write-allocate(?) L1 write policy 4 clock cycles, pipelined L1 hit time (load-use) 1 clock cycle Unified (instruction and data) per core L2 cache organization Unified (instruction and data) 256 KiB (0.25 MiB) 128 KiB to 1 MiB L2 cache size 8-way set associative L2 cache associativity 8-way set associative Approximated LRU Random L2 replacement 64 bytes 64 bytes L2 block size Write-back, Write-allocate L2 write policy Write-back, Write-allocate 11 clock cycles 10 clock cycles L2 hit time L3 cache organization Unified (instruction and data) L3 cache size 8 MiB, shared L3 cache associativity 16-way set associative L3 replacement Approximated LRU L3 block size 64 bytes L3 write policy Write-back, Write-allocate L3 hit time 35 clock cycles FIGURE 5.44 Caches in the ARM Cortex-A8 and Intel Core i7 920.Explanation / Answer
Characteristic
ARM Cotex-A53
Intel Core i7-920
L1 Cache Organization
Split Instruction and data caches
Split instruction, associative data caches
L1 Cache Size
32 kiB each for instruction / data
4 x 32 KB 8-way set associative instruction caches
L1 Cache associativity
4-way(I), 4-Way(D) set accociative
Four way (I), eight-way (D) associativity
L1 Replacement
Random
Approximated LRU
L1 Block Size
64 bytes
64 bytes
L1 Write Policy
Write-back, variable allocation plicies (default is write-allocate)
Write back, no write allocate
L1 hit time (load-use)
Two clock cycles
Four clock cycles, pipelined
L2 Cache Organization
Unified (instruction and data)
Unified (instruction and data) per core
L2 Cache Size
128 KiB to MiB
4 x 256 KB 8-way set associative caches
L2 Cache associativity
16-way set associative
8-way set associative
L2 Replacement
Approximated LRU
Approximated LRU
L2 Block size
64 Bytes
64 Bytes
L2 Write Policy
Write-back, write-allocate
Write back, write allocate
L2 hit time
12 clock cycles
10 clock cycles
L3 Cache Organization
-
Unified (instruction and data)
L3 Cache Size
-
Inclusive shared 8 MB 16-way set associative cache
L3 Cache associativity
-
16-way set associativity
L3 replacement
-
Approximated LRU
L3 Block Size
-
64 Bytes
L3 Write policy
-
Write back, write allocate
L3 hit time
-
35 clock cycles
Characteristic
ARM Cotex-A53
Intel Core i7-920
L1 Cache Organization
Split Instruction and data caches
Split instruction, associative data caches
L1 Cache Size
32 kiB each for instruction / data
4 x 32 KB 8-way set associative instruction caches
L1 Cache associativity
4-way(I), 4-Way(D) set accociative
Four way (I), eight-way (D) associativity
L1 Replacement
Random
Approximated LRU
L1 Block Size
64 bytes
64 bytes
L1 Write Policy
Write-back, variable allocation plicies (default is write-allocate)
Write back, no write allocate
L1 hit time (load-use)
Two clock cycles
Four clock cycles, pipelined
L2 Cache Organization
Unified (instruction and data)
Unified (instruction and data) per core
L2 Cache Size
128 KiB to MiB
4 x 256 KB 8-way set associative caches
L2 Cache associativity
16-way set associative
8-way set associative
L2 Replacement
Approximated LRU
Approximated LRU
L2 Block size
64 Bytes
64 Bytes
L2 Write Policy
Write-back, write-allocate
Write back, write allocate
L2 hit time
12 clock cycles
10 clock cycles
L3 Cache Organization
-
Unified (instruction and data)
L3 Cache Size
-
Inclusive shared 8 MB 16-way set associative cache
L3 Cache associativity
-
16-way set associativity
L3 replacement
-
Approximated LRU
L3 Block Size
-
64 Bytes
L3 Write policy
-
Write back, write allocate
L3 hit time
-
35 clock cycles
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