For this problem, we will examine the performance of the TLB only, so ignore cac

Question

For this problem, we will examine the performance of the TLB only, so ignore cache accesses. Our system has the following properties: 16-bit virtual addresses Page size of 256 bytes 8 entry fully associative TLB Assuming that the TLB has just been flushed (all entries set to invalid), answer the following questions for data accesses in the following code only (i.e. ignore instruction fetches). # define ARAY_SIZE 512 #define LEAP 4 int I; long nums [ARRAY_SIZE];//&nums; = 0 times 0100 (virtual addr) for (I = 0; I

Explanation / Answer

Here array is of long data type long requires 4 bytes

Therefore total 512*4=2048 memory will required.

In one page 256/4=64 elements will be fit.

The page offset for the beginning of array is 0x0000.

The total numbers of pages in array span is 2048/256=8 pages.

Stride is difference between two consecutive elements in array.

Therefore stride is 4 bytes .If the systsem having 32 bit archietcture support the padding.

Then strides is 8 bytes.

128 data accesses occur in each loop.

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