please show a screen shot of the simulation result ! present a timing diagram wh
ID: 3853037 • Letter: P
Question
please show a screen shot of the simulation result !
present a timing diagram which shows the code works
Thank you
The state diagram of a 0101 sequence detector is shown in the following. Assume that the detector starts in state S0 and that S2 is the accepting state. The labels on the arrow indicate the input/output associated with the indicated transitions. Develop a VHDL model for the sequence detector described above. Simulate the model using Quartus software. Present a timing diagram of your simulation showing that it works.Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--Sequence detectr to detecting the sequence "1011".
--Non-overlapping type.
entity seq_det is
port( clk : in std_logic; --clock-signal
reset : in std_logic; --reset-signal
seq : in std_logic; --serial bit sequence
det_vld : out std_logic --A '1' indicates the pattern "1011" is detected in the sequence.
);
end seq_det;
architecture Behavioral of seq_det is
type state_type is (A,B,C,D); --Defines which type for states in the state machine
signal state : state_type := A; --Declare signal with the corresponding state type.
begin
process(clk)
begin
if( reset = '1' ) then --resets states and output signal when reset is asserted.
det_vld <= '0';
state <= A;
elsif ( rising_edge(clk) ) then --calculates the next state based on current state as well as input bit.
case state is
when A => --when control is in state is A.
det_vld <= '0';
if ( seq = '0' ) then
state <= A;
else
state <= B;
end if;
when B => --when control is in state is B.
if ( seq = '0' ) then
state <= C;
else
state <= B;
end if;
when C => --when control is in state is C.
if ( seq = '0' ) then
state <= A;
else
state <= D;
end if;
when D => --when control is in state is D.
if ( seq = '0' ) then
state <= C;
else
state <= A;
det_vld <= '1'; --Output is asserted when the pattern "1011" is found in the sequence.
end if;
when others =>
NULL;
end case;
end if;
end process;
end Behavioral;
Above code corrsponds to a melay machine. For testing the design is given below.It sends a sequence of bits "1101110101" to the module.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY blog_cg IS
END blog_cg;
ARCHITECTURE behavior OF blog_cg IS
signal clock,reset,sequence,det_vld : std_logic := '0';
constant clk_period : time := 10 ns;
BEGIN
-- Intntiate the UnitUnderTest (UUT)
uut: entity work.seq_det PORT MAP (
clock => clock,
reset => reset,
seq => seq,
det_vld => det_vld
);
--Clock process definition
clk_process :process
begin
clock <= '0';
wait for clk_period/2;
clock <= '1';
wait for clk_period/2;
end process;
-- Stimulusprocess : Apply the bits in the sequence one by one.
stim_proc: process
begin
sequence <= '1'; --1
wait for clk_period;
sequence <= '1'; --11
wait for clk_period;
sequence <= '0'; --110
wait for clk_period;
sequence <= '1'; --1101
wait for clk_period;
sequence <= '1'; --11011
wait for clk_period;
sequence <= '1'; --110111
wait for clk_period;
sequence <= '0'; --1101110
wait for clk_period;
sequence <= '1'; --11011101
wait for clk_period;
sequence <= '0'; --110111010
wait for clk_period;
sequence <= '1'; --1101110101
wait for clk_period;
wait;
end process;
END;
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