Consider a byte addressable memory with 12 bit addresses. A cache is used with t

Question

Consider a byte addressable memory with 12 bit addresses. A cache is used with the following characteristics: cache size is 32 bytes block size is 4 bytes number of sets is 4 cache uses the LRU replacement policy Consider an array of integers accessed in the following order (where the array begins at address 0 times 100): arr [theta], arr [4], arr[8], arr[4], arr[theta] 1. The first access to arr[0] would be cold miss 2. The first access to arr[4] would be cold miss 3. The first access to arr[8] would be capacity miss 4. The second access to arr [4] would be hit 5. The second access to arr[o] would be conflict miss

Explanation / Answer

1.) First access to arr[0] would be cold miss, because nothing is there in the cache and the value will be stored at set 1

2.) First access to arr[4] would be cold miss,  because arr[4] is not there in the cache and the value will be stored at set 2

3.) First access to arr[4] would be capacity miss, because array index is starting from 0 which means that address of arr[8] will start from 33rd byte and cache size is 32.

4.) The second access to arr[4] would be hit, because arr[4] is still there in the cache.

5.) The second access to arr[0] would be hit, because arr[0] is still there in the cache.

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