Can anyone help me please!!! I have this code for a serial BCD to excess-3 code

Question

Can anyone help me please!!!

I have this code for a serial BCD to excess-3 code converter and I want someone to help me write the test bench for this code pleaseeee!!!!!!!

Here is the code:

module BCD_Excess3(input B_in,clk,reset_b,output reg B_out);

parameter S0=4'b0000,
S1=4'b0001,
           S2=4'b0010,
           S3=4'b0011,
           S4=4'b0100,
S5=4'b0101,
           S6=4'b0110,
           dont_care_state=4'bx,
           dont_care_out=1'bx;

reg [2:0] state,next_state;

always@(posedge clk,negedge reset_b)

if(reset_b==0) state <=S0;else state <=next_state;

always@(state,B_in)begin

B_out=0;

case(state)

S0:if(B_in==0)begin next_state=S1;B_out=1; end
else if(B_in==1)begin next_state=S2; end

S1:if(B_in==0)begin next_state=S3;B_out=1; end
else if(B_in==1)begin next_state=S4; end

S2:begin next_state=S4;B_out=B_in; end

S3:begin next_state=S5;B_out=B_in; end

S4:if(B_in==0)begin next_state=S5;
B_out=1; end
else if(B_in==1)begin next_state=S6; end

S5:begin next_state=S0;B_out=B_in; end

S6:begin next_state=S0;B_out=1; end

default:begin next_state=dont_care_state;B_out=dont_care_out; end

endcase
end

endmodule

Explanation / Answer

library ieee;
use ieee.std_logic_1164.all;

entity BCD_XS3_tb is
end BCD_XS3_tb;

architecture tb of BCD_XS3_tb is

   component BCD_XS3 is
      port( I,j,k,l : in std_logic;
            a,b,c,d : out std_logic);
   end component;

   signali,j,k,l,a,b,c,d: std_logic;

begin
   mapping: BCD_XS3 port map(I,j,k,l    a,,b,c,d);

   process
      variable errCnt : integer := 0;
   begin

   --TEST 1
      i <= '0';
      j <= '0';
      k <= '0';
      l <= '0';
      wait for 10 ns;
      assert(a = '0') report "a error 1" error;
      assert(b = '0') report "b error 1" error;
      assert(c = '1') report "c error 1" error;
      assert(d = '1') report "d error 1" error;

      if(a /= '0' or b /= '0' or c /= '1' or d /= '1') then
         errorCount := errorCount + 1;
      end if;
      
   --TEST 2
      i <= '0';
      j <= '0';
      k<= '1';
      l <= '0';
      wait for 10 ns;
      assert(a = '0') report "a error 2" error;
      assert(b = '1') report "b error 2" error;
      assert(c = '0') report "c error 2" error;
      assert(d = '1') report "d error 2" error;

      if(a /= '0' or b /= '1' or c/= '0' or d /= '1')
then
         errorCount := errorCount + 1;
      end if;
      
   --TEST 3
      i <= '1';
      j <= '0';
      k <= '0';
      l <= '1';
      wait for 10 ns;
      assert(a = '1') report "a error 3" error;
      assert(b = '1') report "b error 3" error;
      assert(c = '0') report "c error 3" error;
      assert(d= '0') report "d error 3" error;

       if(a /= '1' or b /= '1' or c /= '0' or d/= '0')
then
         errorCount := errorCount + 1;
      end if;
  
    

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