What is the period of the fastest allowable clock for this processor hardware de

Question

What is the period of the fastest allowable clock for this processor hardware design?

Given this processor hardware design, suppose that the following control state is the limiting factor in determining the maximum clock speed. Given that the propagation delay associated with SELrd is 8ns. REGout is 4ns. ALUsub is 16ns. zin is Ins. and r-lORin is 2ns. what is the period (in nanoseconds) of the fastest allowable clock? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here: Zin, SELrd, REGout, MDRin, ALUsub

Explanation / Answer

There are two circuit paths:

SELrd->REGout->MARin delay 8+2+4=14
SELrd->REGout->ALUadd->Zin delay 8+2+16+1=27

27>14, so we need a clock >=27ns period.

Related Questions

Navigate

• Browse (All)
• Browse W
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.