[10/10/15/15/15/20] <B.1> We compare the write bandwidth requirements of write-t

Question

[10/10/15/15/15/20] <B.1> We compare the write bandwidth requirements of
write-through versus write-back caches using a concrete example. Let us assume
that we have a 64 KB cache with a line size of 32 bytes. The cache will allocate a
line on a write miss. If configured as a write-back cache, it will write back the
whole dirty line if it needs to be replaced. We will also assume that the cache is
connected to the lower level in the hierarchy through a 64-bit-wide (8-byte-wide)
bus. The number of CPU cycles for a B-bytes write access on this bus is

the same formula a 12-byte write would take 15 cycles. Answer the following
questions while referring to the C code snippet below:
…
#define PORTION 1 … Base = 8*i; for (unsigned int j=base;
j < base+PORTION; j++) //assume j is stored in a register
data[j] = j;
a. [10] <B.1> For a write-through cache, how many CPU cycles are spent on
write transfers to the memory for the all the combined iterations of the j loop?
b. [10] <B.1> If the cache is configured as a write-back cache, how many CPU
cycles are spent on writing back a cache line?

Explanation / Answer

a)
In your quetion..there is one iteration in loop.
Since base = 8*i (given in question)
according to formula

10 + 5(8/8 - 1) = 10 cycles

b)
If it is write back cache....base will be doubled
So when substitute in formula
10 + 5(16/8 - 1) = 10+5 = 15 cycles

Related Questions

Navigate

• Browse (All)
• Browse #
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.