2. /Siift registers, 4 pts Write the VHDL code (libraries, entity, architecture)
ID: 2250244 • Letter: 2
Question
2. /Siift registers, 4 pts Write the VHDL code (libraries, entity, architecture) for an N-bit "super" register that responds to 3 control bits, AAA. N should be defined as an entity, as a generic with a default value of 8. The operation of the register is as follows: Action state 0 0Shift left 0 Shift right 0 1Synchronous clear set all values to zero) 1OSynchronous set (set all values to onc) 1 OCount up 11Count down When shifting left, input bit LSI should be put in the LSB; when shifting right, input bit RSI should be put into the MSB. The register has an N-bit input, D, and n N-bit guput QThe block diagram of the super register is shown below. RSIExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity super_reg is
generic (N : integer := 8);
port (D : in std_logic_vector (N-1 downto 0);
rsi, lsi : in std_logic;
clk : in std_logic;
A : in std_logic_vector (2 downto 0);
Q : inout std_logic_vector (N-1 downto 0)
);
end super_reg;
architecture arch of super_reg is
begin
process (clk, A, D, lsi, rsi)
begin
if rising_edge (clk) then
case A is
when “000”=> Q <= Q;
when “001”=> Q <= D(N-2 downto 0) & lsi;
when “010”=> Q <= rsi & D(N-1 downto 1);
when “011”=> Q <= (others => ‘0’);
when “100”=> Q <= (others => ‘1’);
when “101”=> Q <= Q + 1;
when “110”=> Q <= Q – 1;
when “111”=> Q <= D;
when others=> null;
end case;
end if;
end process;
end arch;
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