Can someone help me explain what happen? Im simulating a 15 stage ring oscillato

Question

Can someone help me explain what happen? Im simulating a 15 stage ring oscillator, the first image is with propagation delay of 77ps while the second image is 51ps. My question is why the ouput waveform of 77ps delay get like that instead like 51ps which is desired output of the waveform ? Second question is during the time before my enable start to active, why there still output waveform generate at each of the inverter stage? Really appreciate if someone could help me with this. Thanks a lot. Btw im using Xilinx ISE 13.3 Project navigator.

Explanation / Answer

(i) In a ring counter, each flop in the chain is fed by its preceding flip flop. For a n-stage ring counters if the signal assignment statement are written in the process block then all the statements gets executed sequentially which is not the case in hardware. Check your clock frequency. Try structural modelling/concurrent signal assignments. Sharing your code with spec will provide more insight.

(ii) There is a problem in the coding seems, as we need every signal to be synchronized with the clock unless asynchronous reset/clr etc. is required.

Can se enable signal toggling like a clock in the absence of actual clock. In practice its not expected.

Process(clk)

if rising_edge(clk) then

if (en = '1') then --- synchronized to clock

---statements

else

--- do nothing/retain previous statements like Q <= Q;

end if;

end if;

end process;

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