3. (10 points) Calculate the power reduction of a computation if it is pipelined

Question

3. (10 points) Calculate the power reduction of a computation if it is pipelined by 4 stages and processed using a block structure with block size 4, ut is operated with the same sample rate as the original system. Assume that the original system was operated at a supply voltage of 5V, and assume the threshold voltage V, of the CMOS process to be 0.4V. Calculate the power consumption of the parallel-pipelined system as compared with the original system. What is the operating supply voltage of the parallel- pipelined system?

Explanation / Answer

Power consumption is original system

Supply =5V

Vt =0.4 V

Pipelined initially by 4 stages :

Since same sample rate

Let Power initially is VI= 5I

Since i is in series hence I is same

And power reducted to = 5I- 4(0.4 I)

=3.4 I

Power reduction = (5-3.4 )/ 5 * 100%

=32 %

In Parallel Pipelined system

Power consumotion by individual is :

Pi=Vt*I/4

Since current distributed equally in all the 4

Hence , Total Power consumed =4*Vt*I/4

=4*0.4*I/4

=0.4I

Hence power reduced to = 5I-0.4 I

=4.6 I

Total reduction in power =( 5-0.4)/5*100

=8 %

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