Question are ture or false. I\'m having trouble how to read the tables thus find
ID: 3534402 • Letter: Q
Question
Question are ture or false. I'm having trouble how to read the tables thus finding the questions hard. If somone can show how they got T or F would be awesome.
You have a virtual memory system with a two-entry TLB, a 2-way set associative cache and a page table for a process P. Assume cache blocks of 8 bytes and page size of 16 bytes. In the system below, main memory is divided up into blocks, where each block is represented by a letter. Two blocks equals one frame.
1) Virtual address page 5, offset 4 results in a TLB miss and a page table hit.
2) Virtual address page 0, offset 3 results in a page fault.
3) Virtual address page 0 offset 0 is a TLB hit and a cache miss.
4) Physical address Block 6 results in a cache miss.
5) Virtual address page 7, offset 1 results in a TLB hit.
Explanation / Answer
How many bits are in a virtual address for process P? Explain.
b. How many bits are in a physical address? Explain. c.
Show the address format for virtual address 1810 (specify field name and size) that would be used by the system to translate to a physical address and then translate this virtual address into the corresponding physical address. (Hint: convert 18 to its binary equivalent and divide it into the appropriate fields.) Explain how these fields are used to translate to the corresponding physical address.
Given virtual address 610 converts to physical address 5410. Show the format for a physical address (specify the field names and sizes) that is used to determine the cache location for this address. Explain how to use this format to determine where physical address 54 would be located in cache. (Hint: convert 54 to binary and divide it into the appropriate fields.)
e. Given virtual address 2510 is located on virtual page 1, offset 9. Indicate exactly how this address would be translated to its corresponding physical address and how the data would be accessed. Include in your explanation how the TLB, Page Table, Cache and Memory are used.
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