What will be the logic levels on the external SRC buseswhen each of the given SR
ID: 3618616 • Letter: W
Question
What will be the logic levels on the external SRC buseswhen each of the given SRC instruction is executing on theprocessor? Complete Table: A all numbers are in the decimal numbersystem, unless noted otherwise. (Assume the required missinginformation if necessary). Also Specify memory addressingmodes for each of the SRC instructions given in Table.
SRC instruction
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r7,12(r3)
Ld r1,4
Ld r6, M[r3]
Move r2, r9
Table: A
Assumptions:
SRC instruction
RTL Equivalent
Address Bus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r7,12(r3)
Ld r1,4
Ld r6, M[r3]
Move r2, r9
Explanation / Answer
SRC instruction
RTL Equivalent
AddressBus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r7,12(r3)
R[7]ßM[12+R[3]]
unknown
????
?
?
Register
Ld r1,4
R[1]ßM[4]
unknown
????
?
?
Register
Ld r6, M[r3]
R[6]ßM[R[3]]
unknown
???
?
?
Register
Move r2, r9
R[2]ßR[9]
unknown
????
?
?
Register
SRC instruction
RTL Equivalent
AddressBus<31….0>
Data Bus
<31….0>
MRead
MWrite
Addressing mode
Ld r7,12(r3)
R[7]ßM[12+R[3]]
unknown
????
?
?
Register
Ld r1,4
R[1]ßM[4]
unknown
????
?
?
Register
Ld r6, M[r3]
R[6]ßM[R[3]]
unknown
???
?
?
Register
Move r2, r9
R[2]ßR[9]
unknown
????
?
?
Register
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.