What will be the logic levels on the external SRC buseswhen each of the given SR

Question

What will be the logic levels on the external SRC buseswhen each of the given SRC instruction is executing on theprocessor? Complete Table: A all numbers are in the decimal numbersystem, unless noted otherwise. (Assume the required missinginformation if necessary). Also Specify memory addressingmodes for each of the SRC instructions given in Table.

SRC instruction

RTL Equivalent

Address Bus<31….0>

Data Bus

<31….0>

MRead

MWrite

Addressing mode

Ld r7,12(r3)

Ld r1,4

Ld r6, M[r3]

Move r2, r9

Table: A

Assumptions:

Memory map with assumedvalues

SRC instruction

RTL Equivalent

Address Bus<31….0>

Data Bus

<31….0>

MRead

MWrite

Addressing mode

Ld r7,12(r3)

Ld r1,4

Ld r6, M[r3]

Move r2, r9

Explanation / Answer

SRC Instruction

RTL Equilent

Address bus<31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

0

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

0

(b) Specify memory addressing modes for each of the SRCinstructions given in Table.

Solution:-

Memory Addressing

SRC Instruction

LD r7,12(r5)

LD r2,16

Addressing Mode

Displacement

Direct

SRC Instruction

RTL Equilent

Address bus<31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

0

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

0

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