Compare the performance (using AMAT) of a one-level split cache and a two-level

Question

Compare the performance (using AMAT) of a one-level split cache and a two-level unified cache system. For the one-level split cache, suppose a hit takes 2 clock cycles and the miss penalty is 100 clock cycles. Assume 20% memory accesses are data transfer. In 1000 memory references there are 20 misses for the instruction cache, and 50 misses for the data cache. In the two-level cache, assume that the miss rates for the L1 cache and the L2 caches are 5% and 2%, respectively. Assume the miss penalty from the L2 cache to memory is 100 cycles, the hit times of the L1 and L2 caches are 1 and 10 clock cycles, respectively. [Split cache: a scheme in which a level of the memory hierarchy is composed of two independent caches that operate in parallel with each other, with one handling instructions and one handling data.]

Explanation / Answer

    Hit time = 2clock cycles

    Miss penalty=100clock cycles

   Instruction miss rate = 20/1000

                                    =2%       

   Data miss rate =50/1000

                           =5%

Miss rate for L1 =5%

  Miss rate for L2 =2%

  Miss penalty for L2 =100cycles

Hit time for L1 =1cycle

Hit time for L2 =10cycles

Average access time (split)

     = % instructions x (Hit time + Instruction miss rate x Miss Penalty)

     + % data x (Hit time + Instruction miss rate x Miss Penalty)

   = 20% x (2+2% x100) +80% x (1+5% x 100)

   = 0.2 x(2+0.02 x100)+0.8 x(1+0.05 x100)

= 0.2 x(4)+0.8(6)

=0.8+4.8

=5.6

Average access time (unified)

    = Hit time(L1)+Miss rate(L1)x(Hit time(L2)+Miss rate(L2) x miss penalty(L2)

    = 1+5% x(10+2% x100)

    =1+0.05 x(10+0.02 x100)

    =1+0.05 x(12)

    =1+0.6

    =1.6

Related Questions

Navigate

• Browse (All)
• Browse C
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.