8.) Consider the following 5-stage pipeline: JElInstruction fetchl, ID[instructi

Question

8.) Consider the following 5-stage pipeline: JElInstruction fetchl, ID[instruction decoder], EX[execute], DMIdata memoryl, WB[write back] The register file can read and write in the same cycle Instruction Fetch Instruction Decode Execute Data Memory Writeback Time 200 4006001 800 1000 1200 Instruction1 Instruction Instruction 3 MEM MEM Clock Cycle 1 2 Instruction 1: ? M[10] Instruction 2: BI21R(15)-RIS Instruction 3: B13] ? R[7] + R[5] 9.) True or False Two Instructions could possibly need to use the ALU simultaneously. 10.)True or False Two instructions could possibly need to use the register file during the same clock cycle. 11.)What is the maximum number of instructions that could possibly be executing during one clock cycle in this 5

Explanation / Answer

9)yes true,two or more instructions can possible to use the same ALU simultaneously.ALU can have the property of multiple instructions

10)during same clock cycle two instructions can use the register file while read mode.but in write mode this is not possible.because there may cause some internal error.

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