Below is a list of 32-bit memory address references, given as byte addresses. 21
ID: 3830718 • Letter: B
Question
Below is a list of 32-bit memory address references, given as byte addresses. 21, 166, 201, 143, 61, 166, 62, 133, 111, 143, 144, 61
(a) For each of these references, identify the binary address, the tag, and the index given a direct-mapped cache with four-byte blocks and a total size of 32 bytes. Also list if each reference is a hit or a miss, assuming the cache is initially empty
(b) Show the cache contents (by listing the tags that are currently in the cache) for a fully associative cache withwith four-byte blocks and a total size of 16 bytes, using LRU replacement. For each reference identify the tag bits, and if it is a hit or a miss. What is the miss rate?
(c) For each reference identify the index bits, the tag bits, and if it is a hit or a miss for a two-way set associative cache with two-byte blocks and a total size of 32 bytes. Show the final cache contents (by listing the tags that are currently in the cache). Use LRU replacement.
Decimal Address Binary Address Tag Index Hit/Miss 166 143 166 143 144Explanation / Answer
For Direct mapped cache
Given:
4 byte blocks, so block offset is log(4) or 2 bits
Cache size is 32byte, so we have 32/4 or 8 blocks. Therefore for directly mapped cache index field would be log(8) or 3 bits wide.
Decimal Add
Binary Add
Tag
Index
Hit/Miss
21
0001 0101
000
101
Miss
166
1010 0110
101
001
Miss
201
1100 1001
110
010
Miss
143
1000 1111
100
011
Miss
61
0011 1101
001
111
Miss
166
1010 0110
101
001
Hit
62
0011 1110
001
111
Hit
133
1000 0101
100
001
Miss
111
0110 1111
011
011
Miss
143
1000 1111
100
011
Miss
144
1001 0000
100
100
Miss
61
0011 1101
001
111
Hit
For Fully associative memory:
Given:
4 byte blocks, so block offset is log(4) or 2 bits
Cache size is 16byte, so we have 16/4 or 4 blocks.
Decimal Add
Binary Add
Tag
Hit/Miss
Contents
21
0001 0101
00 0101
Miss
Block 0
166
1010 0110
10 1001
Miss
Block 1
201
1100 1001
11 0010
Miss
Block 2
143
1000 1111
10 0011
Miss
Block 3
61
0011 1101
00 1111
Miss
Block 0
166
1010 0110
10 1001
Hit
Block 1
62
0011 1110
00 1111
Hit
Block 0
133
1000 0101
10 0001
Miss
Block 2
111
0110 1111
01 1011
Miss
Block 3
143
1000 1111
10 0011
Miss
Block 1 (LRU is 1)
144
1001 0000
10 0100
Miss
Block 0
61
0011 1101
00 1111
Miss
Block 2
For 2-way set associative cache:
Given:
2 byte blocks, so block offset is log(2) or 1 bits
Cache size is 32byte, so we have 32/2 or 16 blocks and 16/2 or 8 sets. Therefore for directly mapped cache index field would be log(8) or 3 bits wide.
Decimal Add
Binary Add
Tag
Set
Way
Hit/Miss
21
0001 0101
0001
010
0
Miss
166
1010 0110
1010
011
0
Miss
201
1100 1001
1100
100
0
Miss
143
1000 1111
1000
111
0
Miss
61
0011 1101
0011
110
0
Miss
166
1010 0110
1010
011
0
Hit
62
0011 1110
0011
111
1
Miss
133
1000 0101
1000
010
1
Miss
111
0110 1111
0110
111
0
Miss
143
1000 1111
1000
111
1
Miss
144
1001 0000
1001
000
0
Miss
61
0011 1101
0011
110
1
Miss
So here you go champ. I have filled all the table you have provided. I have also mentioned the reason for few of them. Please go through the table and let me know if you have any confusion. I shall try my best to guide you through the process where you are having trouble.
Decimal Add
Binary Add
Tag
Index
Hit/Miss
21
0001 0101
000
101
Miss
166
1010 0110
101
001
Miss
201
1100 1001
110
010
Miss
143
1000 1111
100
011
Miss
61
0011 1101
001
111
Miss
166
1010 0110
101
001
Hit
62
0011 1110
001
111
Hit
133
1000 0101
100
001
Miss
111
0110 1111
011
011
Miss
143
1000 1111
100
011
Miss
144
1001 0000
100
100
Miss
61
0011 1101
001
111
Hit
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