Consider the 8T SRAM cell given below. With this design, there is a Write Word L

Question

Consider the 8T SRAM cell given below. With this design, there is a Write Word Line (WWL) that is used to write the values of Write Bit Line (WBL) and WBL into the cell, and a separate Read Word Line (RWL) that is used to read the content of the cell on the Read Bit Line (RBL). a) Determine which transistors are involved in a Write operation, and comment on their relative sizing. b) For the same cell, determine which transistors are involved in a Read operation, and comment on their relative sizing. c) Compare this structure with the 6T SRAM cell. What are the advantages and disadvantages?

Explanation / Answer

(A) As we all know, Gate voltage of proper value is needed to excite a transistor. According to this diagram, WWL line directly supplies (controls) gate voltage to two NMOS transistors AXL and AXR.

Now, AXL accepts writing data from WBL line and AXR accepts the data from WBL' (' is equivalent to complement _) line. Since both AXL and AXR are NMOS transistors and they are excited by the same gate voltage, their speed of operation will be same and consequently their relative size will also be same.

AXL and AXR are connected to some other transistors such as PL, PR, NL and NR in order to complete the right operation. PL and PR are PMOS transistors and their speed of operation will be naturally smaller than NL and NR, the two NMOS transistors. To mach up the speed, their (W/L) ratio [Width/Length ratio] must be controlled.

(B) RWL line directly excites the GATE terminal of N0 and N1 gets the data written from the WBL line by the transistor AXL into the CMOS formed by PR and NR. The output of this CMOS i.e. the data coming from the line WBL is used to excite the gate of the transistor N1. Finally the data of N1 is written or places on the RBL line.

Since both N0 and N1 are NMOS transistors, their size is exactly same.

(C).

The main advantage of 6T SRAM design over 8T is low static power dissipation.

But the main disadvantage of this architecture comes in the form of data misinterpretation. During read opertion, a stored '0' can be read as '1'.

To overcome this problem, in 8T SRAM, seperate read/write bit lines and word lines are used.

Hope this helpes

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