Consider a CPU that implements two parallel fetch-execute pipelines for supersca

Question

Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming an instruction cycle similar to figure 4.1 in the commentary, i.e.:
• a one clock cycle fetch
• a one clock cycle decode
• a four clock cycle execute
and a 40 instruction sequence:

• no pipelining would require _____ clock cycles:


• a scalar pipeline would require _____ clock cycles:


• a superscalar pipeline with two parallel units would require ______ clock cycles:

Explanation / Answer

Note that the step: PC + 1 ? PC is performed early because it doesn't affect the calculation. Also, these steps: IR[opcode] ? decoder and IR[address] ? MAR are performed in parallel. Performing the steps in parallel reduces the number of clock cycles a = 1 b = 2 3= c 4= d 5= e 6=f 7 = g time-------- A: PC ----mar D: IR(opcode) ----decoder G: next instruction IR [address] ----MDR B: PC + 1 ------PC E: Mem [mar]-------mdr Mem[(MAR) -----MDR f: A + MDR ____ a C: mdr ---------ir

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