Consider a CPU that implements two parallel fetch-execute pipelines for supersca

Question

Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing assuming an instruction cycle, i,e:
• a one clock cycle fetch
• a one clock cycle decode
• a two clock cycle execute
and an 80 instruction sequence:

• no pipelining would require _____ clock cycles:

• a scalar pipeline would require _____ clock cycles:

• a superscalar pipeline with two parallel units would require ______ clock cycles:

Explanation / Answer

If pipelining is used, then sequence instructions are fetched, decoded, and executed in parallel. If one instruction is being decoded, then the next instruction is being fetched. If the first instruction is being executed, Then the second instruction is being decoded and a third instruction is being fetched. If the four different instructions are performing at the same time after pulse 4: instruction 1 is on step 4 instruction 2 is on step 3 instruction 3 is on step 2 instruction 4 is on step 1

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