Consider a CPU that implements two parallel fetch-execute pipelines for supersca

Question

Consider a CPU that implements two parallel fetch-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle below: a one clock cycle fetch a one clock cycle decode a three clock cycle execute and a 50 instruction sequence: No pipelining would require___clock cycles: A scalar pipeline would require___clock cycles: A superscalar pipeline with two parallel units would require___clock cycles:

Explanation / Answer

4.

No pipelining would require _____clock cycles:

According to the above information

(1 fetch, 1 decode and 2 execute) if its a non pipelined processor, then that requires 4 clock

cycles per instruction. So the total clock cycles = 4 x 60 = 240 Clock cycles for the instruction

sequence.

5. A scalar pipeline would require _____ clock cycles:

When pipelined, it requires 60 x 1 = 60

clock cycles

6. A superscalar pipeline with four parallel units would require ______ clock cycles: when you implement 4 x super scalar pipeline, it requires 60 x ¼ = 15 clock cycles

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