(a) What will be thelogic levels on the external SRC buses when each of the give

Question

      (a) What will be thelogic levels on the external SRC buses when each of the given SRCinstruction is
executing on the processor? Complete Table:A all numbers are in thedecimal number system, unless
noted otherwise. (Assume the required missing information ifnecessary)
(b) Specify memory addressing modes for each of the SRCinstructions given in Table.
SRC
instruction
RTL Equivalent Address
Bus<31….0>
Data Bus
<31….0>
MRead MWrite
Ld
r3,12(r5)
Ld r2,16
Table: A
Assumptions:
• All memory content is aligned properly.
• In other words, all the memory accesses start at addressesdivisible by 4.
• Value in the PC = 000DC348h
Memory map with assumed values
Register map with assumed values

Explanation / Answer

Solution:-

SRC Instruction

RTL Equilent

Address bus<31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

0

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

0

(b) Specify memoryaddressing modes for each of the SRC instructions given inTable.

Solution:-

MemoryAddressing

SRC Instruction

LD r7,12(r5)

LD r2,16

Addressing Mode

Displacement

Direct

SRC Instruction

RTL Equilent

Address bus<31 0>

Data bus

<31   0>

M(R)

M(W)

LD r3,12(r5)

R[3]<-M[12+R[5]

00AB1240h

0785E530h

1

0

LD r2,16

R[2]<-M[16]

00000020h

D296492fh

1

0

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