Consider a program that can execute with no stalls and a CPI of 1 if the underly

Question

Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 10% of all load instructions suffer from an L1 cache miss, and 2% of all load instructions suffer from an L2 cache miss (and are serviced by the memory system). An L1 cache miss stalls the processor for 20 cycles while the L2 is looked up. An L2 cache miss stalls the processor for an additional 250 cycles while data is fetched from memory. What is the CPI for this program if 20% of the program's instructions are load instructions?

Explanation / Answer

Answer:

=> Split L1 by means of no strike punishment, (i.e., the right of entry occasion is the occasion it takes to execute the load/amass teaching

=> L1 I-cache: 2% fail to spot rate, 32-byte blocks (require 2 bus cycle to fill, miss punishment is 15ns +2 cycles

The standard reminiscence right of entry time for teaching accesses:

L1 (inst) miss occasion in L2: 15ns right of entry time advantage two L2 cycle (two = 32 bytes in inst.

=> Cache line/16 bytes breadth of L2 means of transportation) = 15 + 2 × 3.75 = 22.5ns. (3.75 is equivalent to single 266 MHz L2 cache cycle)

L2 miss occasion in reminiscence: 60ns + plus four reminiscence cycle (four = 64 bytes in L2 cache/16 bytes width of memory bus) =

60 + 4 × 7.5 = 90ns (7.5 is equal to one 133 MHz reminiscence bus cycle).

=> Components: base CPI, Inst fetches CPI, read CPI or inscribes CPI, inst obtain time is added to data

Read or write time (for load/store instructions).

CPI = 0.7 + 1.09 + 0.2 × 1.01 + 0.05 × 2.52 = 2.19 CPI.

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