Consider a program that can execute with no stalls and a CPI of 1 if the underly

Question

Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 10% of all load instructions suffer from an L1 cache miss, and 2% of all load instructions suffer from an L2 cache miss (and are serviced by the memory system). An L1 cache miss stalls the processor for 20 cycles while the L2 is looked up. An L2 cache miss stalls the processor for an additional 250 cycles while data is fetched from memory. What is the CPI for this program if 20% of the program's instructions are load instructions?

Explanation / Answer

=> Split L1 with no hit penalty, (i.e., the access time is the time it takes to execute the load/store instruction
=> L1 I-cache: 2% miss rate, 32-byte blocks (requires 2 bus cycles to fill, miss penalty is 15ns +2 cycles
=> The average memory access time for instruction accesses:
L1 (inst) miss time in L2: 15ns access time plus two L2 cycles ( two = 32 bytes in inst.
=> cache line/16 bytes width of L2 bus) = 15 + 2 × 3.75 = 22.5ns. (3.75 is equivalent to one 266 MHz L2 cache cycle)
L2 miss time in memory: 60ns + plus four memory cycles (four = 64 bytes in L2 cache/16 bytes width of memory bus) =
60 + 4 × 7.5 = 90ns (7.5 is equivalent to one 133 MHz memory bus cycle).

=> Components: base CPI, Inst fetch CPI, read CPI or write CPI, inst fetch time is added to data
read or write time (for load/store instructions).
CPI = 0.7 + 1.09 + 0.2 × 1.01 + 0.05 × 2.52 = 2.19 CPI.

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