Consider a program that can execute with no stalls and a CPI of 1 if the underly

Question

Consider a program that can execute with no stalls and a CPI of 1 if the underlying processor can somehow magically service every load instruction with a 1-cycle L1 cache hit. In practice, 5% of all load instructions suffer from an L1 cache miss, 2% of all load instructions suffer from an L2 cache miss, and 1% of all load instructions suffer from an L3 cache miss (and are serviced by the memory system). An L1 cache miss stalls the processor for 10 cycles while the L2 is looked up. An L2 cache miss stalls the processor for 20 cycles while the L3 is looked up. An L3 cache miss stalls the processor for an additional 300 cycles while data is fetched from memory. What is the CPI for this program if 30% of the program's instructions are load instructions?

Explanation / Answer

Solution:

The CPI will be Consider as

The cycle in use by L1 in case of hit is = 1

hit rate in favor of L1= 0.95

The cycle in use by L2 in casing of hit is = 10

hit rate for L2= 0.98

The cycle in use by L1 in casing of hit is = 20

hit rate for L1= 0.99

penalty for L1 cache miss, L2 miss, L3 miss/ Memory access time=300 cycles

percentage of load instructions=30%=0.3

Rest of instructions =70%= 0.7

CPI= L1 cache hit prospect Time +l1 miss closeness Memory Access time

= 0.9*1 + 0.1*(0.98 * (1+10) + 0.02*(0.99*(1+10+20) + 0.01*(1+10+20+300))

= 2.046

CPI if 100% INSTUCTIONS ARE Load orders, but the load orders being 30%=0.3 * 2.046?

The effectual CPI= 0.6138?

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